1. Field of the Invention
The present invention relates to a time constant automatic adjustment circuit and, more particularly, to a time constant automatic adjustment circuit for a filter circuit incorporated into an IC.
2. Description of the Prior Art
In general, a filter circuit employs a time constant circuit for determining the frequency characteristics of the circuit. The time constant circuit requires that the time constant of the circuit be maintained stably at a predetermined value. A time constant circuit is usually constituted by resistive elements and capacitive elements (or equivalent circuits therefor). When such a filter circuit is fabricated as an integrated circuit (referred to as an IC hereafter), it is necessary to adjust the time constant of the time constant circuit externally, since the resistances or the capacitances of the resistive elements and capacitive elements of the circuits are not precise. Further, the resistances or the capacitances of the resistive elements and capacitive elements of the circuits are unstable in relation to temperature change and long term use.
Referring now to FIGS. 1 to 5, some conventional adjustments for some typical filter circuits or time constant circuits will be explained. FIGS. 1 to 5 show five typical examples of a filter circuit, e.g., a low-pass filter.
First, the filter circuit shown in FIG. 1 has a time constant circuit comprised of a resistor 10 and a variable capacitor 12. The resistor 10 is connected between an input terminal 14 for receiving an input signal Vin and an output terminal 16 for supplying an output signal Vout. The variable capacitor 12 is connected between the output terminal 16 and a control terminal 18 for receiving a control signal Vc for adjustment. According to the connection of the resistor 10 and the variable capacitor 12, the time constant circuit forms a low-pass filter or an integrating circuit. The capacitance of the variable capacitor 12 varies in response to changes in the value of the control signal Vc on the control terminal 18.
The filter circuit shown in FIG. 2 has a time constant circuit comprised of a field effect transistor (referred to as a FET hereafter) 20 and a capacitor 22. The FET 20 is connected between an input terminal 14 for receiving an input signal Vin and an output terminal 16 for supplying an output signal Vout. The capacitor 22 is connected between the output terminal 6 and a reference potential terminal, e.g., the grounded terminal 24. The FET 20 has a gate connected to a control terminal 18 for receiving a control signal Vc for adjustment. The impedance of the FET 20 varies in response to changes of the value of the control signal Vc on the control terminal Vc.
The filter circuit shown in FIG. 3 has a time constant circuit comprised of a bipolar transistor 26, a variable current source 28 and a capacitor 22. The base and the emitter of the bipolar transistor 26 are connected to an input terminal 14 for receiving an input signal Vin and an output terminal 16 for supplying an output signal Vout, respectively. The collector of the bipolar transistor 26 is connected to a power source terminal 30 for receiving a power source voltage Vcc. The variable current source 28 is connected between the emitter of the bipolar transistor 26 and a reference potential terminal, e.g., the grounded terminal 24. The capacitor 22 is connected between the emitter of the bipolar transistor 26 and the grounded terminal 24, i.e., in parallel with the variable current source 28. The variable current source 28 is designed to receive a control signal Vc on a control terminal 18 for adjustment. Thus, the current I28 of the variable current source 28 varies in response to the control signal Vc. The variable current source 28 supplies the bipolar transistor 26 with the variable current I28 in response to the control signal Vc, so that the equivalent emitter resistance of the bipolar transistor 26 is varied. The filter circuits, as shown in FIGS. 1 to 3, have a transfer characteristic G(LPF) as follows: EQU G(LPF)=1/(1+j.multidot.w.multidot.R.multidot.C) (1)
wherein j is the unit imaginary number (.sqroot.-1) angle frequency of the input signal Vin, R is the resistance or impedance of the resistor 10, the FET 20 or the bipolar transistor 26 and C is the capacitance of the variable capacitor 12 or the capacitors 22. The transfer characteristic G(LPF) is influenced by variations in the amplitude of the input signal Vin. That is, When the amplitude of the input signal Vin varies, the variable capacitor 12 (FIG. 1), the FET 20 (FIG. 2 , and the bipolar transistor 26 (FIG. 3) are affected directly by the variation of the input signal Vin. Thus, a distortion is caused in the output signal Vout. As a result, it is difficult for the filter circuits to exhibit their full performance.
The fourth filter circuit shown in FIG. 4 is comprised of two time constant circuits and a buffer amplifier 32 which are connected in series between an input terminal 14 and an output terminal 16. Each of the two time constant circuits has an MOS FET (metal oxide semiconductor field effect transistor) 34a (34b) and a capacitor 22a (22b). The MOS FETs 34a and 34b of the time constant circuits and the buffer amplifier 32 are connected in series between the input terminal 14 and the output terminal 16. The capacitor 22a of the preceding time constant circuit is connected in parallel with the series circuit of the MOS FET 36b and the buffer amplifier 32. The capacitor 22b of the following time constant circuit is connected between the drain of the second MOS FET 34b and a grounded terminal 24.
An input signal Vin on the input terminal 14 is applied to the buffer amplifier 32 through the two time constant circuits in series, and an output signal Vout appears on the output terminal 16. The MOS FETs 34a and 34b are supplied at their gates with a control signal Vc together through a control terminal 18. Resistances R34a and R34b of the MOS FETs 34a and 34b vary in accordance with the control signal Vc fed to their gates. Thus, the time constants T1 and T2 of the time constant circuits can be varied by the control signal Vc.
The transfer function of the fourth filter circuit shown in FIG. 4 is carried out as follows. If the resistances R34a and R34b of the MOS FETs 34a and 34b satisfy the relations R34a=R34b=R34, and the amplification factor K of the buffer amplifier 32 is 1, ##EQU1## wherein S is a constant, i.e., S=1/(j.multidot.w).
Hereupon, if the time constants T1 and T2 of the time constant circuits satisfy the relationships: EQU T1=R34.multidot.C22a, T2=R34.multidot.C22b, (3)
The following is obtained: ##EQU2##
In case the filter circuit is fabricated in the IC configuration, the absolute values of the capacitances C22a and C22b are largely dispersed to the extent of .+-.30% ), but the relative accuracy is good. For example, if the capacitance C22a is enlarged by +10%, the capacitance C22b is enlarged also by +10%. Therefore, against this dispersion, if the gate voltage of the MOS FETs 34a and 34b, i.e. the control signal Vc is regulated, and the resistance R34 is reduced by 10%, the time constants T1 and T2 can be constantly maintained.
The fifth filter circuit, as shown in FIG. 5, has been devised for reducing the distortion in the output signal Vout. The filter circuit shown in FIG. 5 has a time constant circuit comprised of a first differential amplifier circuit 36 and a capacitor 22. The first differential amplifier circuit 36 and the capacitor 22 are connected to each other through a current conversion circuit 38.
In the first differential amplifier circuit 36, a pair of transistors 40, 42 are connected at their collectors to a power source terminal 30 for receiving a power source voltage Vcc, and at their emitters to a grounded terminal 24 through a fixed current source 44. Resistors 46, 48 are connected between the emitters of the transistors 40, 42 and the fixed current source 44. The fixed current source 44 is comprised of a resistor 50 and a pair of transistors 52 and 54. The resistor 50 and the transistor 52 are connected in series between the power source terminal 30 and the grounded terminal 24. The transistor 52 is connected in a diode fashion, and the transistor 54 is connected at its base to the base of transistor 52. Thus, the transistors 52 and 54 are connected in a current mirror configuration. The transistor 54 is connected between the common connection node of the resistors 46 and 48 of the first differential amplifier circuit 36 and the grounded terminal 24. Thus, the series circuit of the resistor 50 and the transistor 52 provides a fixed current I44. The transistor 54 supplies the same current I44 to the first differential amplifier 36.
The base of the transistor 40 of the first differential amplifier circuit 36 is connected to an input terminal 14 for receiving an input signal Vin, while the base of the transistor 42 is connected to an output terminal 6 for supplying an output signal Vout. The current conversion circuit 38 is comprised of six transistors 56, 58 . . . 66, a reference voltage source 68 with a reference voltage V68 and a variable current source 28.
A pair of the transistors 58, 60 in the current conversion circuit 88 are connected at their collectors to the power source terminal 30 together. Their bases are connected to each other and applied with the reference voltage V68 from the reference voltage source 68. Their emitters are connected to the collectors of the transistors 40 and 42 of the first differential amplifier circuit 36, respectively. The transistors 56, 58 thus constitute an active load circuit 70 for the first differential amplifier circuit 36.
Another pair of the transistors 60, 62 in the current conversion circuit 38 are connected at their collectors to the power source terminal 30. Their emitters are connected to each other and then to the grounded terminal 24 through a transistor 72 of the variable current source 28. Their bases are connected to the collectors of the transistors 40 and 42 of the first differential amplifier circuit 36, respectively. The transistors 60 and 62 thus constitute a second differential amplifier circuit 74.
Another pair of the transistors 64, 66 in the current conversion circuit 38 have a PNP configuration in particular and are connected with each other in a current mirror configuration. That is, their bases are connected to each other and then to the collector of the transistor 64. Their emitters are connected to the power source terminal 30. The collector of the transistor 64 is connected to the transistor 62 of the second differential amplifier circuit 74. The transistors 64 and 66 thus constitute a current mirror configuration active load circuit 76 for the second differential amplifier circuit 74. The output of the second differential amplifier circuit 74 is extracted through the current mirror configuration active load circuit 76. The collector of the transistor 66 of the current mirror configuration active load circuit 76 is connected to the grounded terminal 24 through a transistor 78 of the variable current source 28. The collector of the transistor 66 is further connected to the base of a transistor 80.
The collector of the transistor 80 is connected to the power source terminal 30. The emitter of the transistor 80 is connected to an output terminal 16 of the filter circuit. The output terminal 16 is then connected to the grounded terminal 24 through a resistor 82. Further, the output terminal 16 is connected to the base of the transistor 42 of the first differential amplifier circuit 36. Thus, the output voltage Vout on the output terminal 16 is fed back to the first differential amplifier 36.
The variable current source 28 is comprised of a variable resist 84, a transistor 86 and the transistors 72 and 78. The variable resistor 84 and the transistor 86 are connected in series between the power source terminal 30 and the grounded terminal 24. The transistor 86 is connected itself in a diode fashion, and the transistors 72 and 78 are connected at their bases to the base of transistor 86. Thus, the transistor 86 is connected to the transistors 72 and 78 in current mirror configurations, respectively. Thus, the series circuit of the variable resistor 84 and the transistor 86 provides a variable current I28. The transistor 78 has half the emitter area of the emitter areas of the transistors 72 and 86. Thus, the transistor 72 supplies the second differential amplifier 74 with the same current I28. The transistor 78 supplies the active load circuit 76 with a current half that of the current I28.
The capacitor 22 is connected between the base of the transistor 80 and the grounded terminal 24.
The operation of the fifth filter circuit shown in FIG. 5, will now be described in detail.
When an input signal Vin is applied from the input terminal 14 to the base of the transistor 38 of the first differential amplifier circuit 36, collector currents I40 and I42 flow through the transistors 40, 42 of the first differential amplifier 36, respectively. The currents I40 and I42 also flow through the transistors 56, 58 of the active load circuit 70, respectively. Collector currents I60 and I62 flow through the transistors 60 and 62 of the second differential amplifier circuit 74 of the current conversion circuit 38, respectively. Since the bases of the transistors 56, 68 are connected with each other, the currents I40 and I42 have a relation defined by a logarithmic (Ln) characteristic of PN junctions in the transistors 56 and 58. Since the emitters of the transistors 60, 62 are connected with each other, the currents I60 and I62 have a relation defined by an exponential (Exp) characteristic of PN junctions in the transistors 60 and 62. As is well known, the logarithmic (Ln) characteristic and the exponential (Exp) characteristic compensate for each other. Thus, the following relation is maintained between the collector currents I40, I42, I60 and I62: EQU I40/I42=I60/I62 (5)
Thereupon, the collector currents I40, I42, I60 and I62 are able to be expressed as follows:
I40=I44/2+.DELTA.i36 PA1 I42=I44/2-.DELTA.i36 PA1 I60=I28/2+.DELTA.i74 PA1 I62=I28/2-.DELTA.i74
wherein .DELTA.i36 is a variable component of a current flowing through the first differential amplifier 36, and .DELTA.i74 is a variable component of a current flowing through the second differential amplifier 74.
From the above equations, the following equation for the variable component .DELTA.i74 is obtained: EQU .DELTA.i74=(I28/I44).multidot..DELTA.i36
The variable current component .DELTA.i74 flows into the capacitor 22 through the active load 76. Thus, the output signal Vout on the output terminal 16 becomes as follows: ##EQU3## wherein C22 is the capacitance of the capacitor 22.
When this output signal Vout is negatively fed back to the first differential amplifier 36 through the feedback circuit, the variable current component .DELTA.i36 of the first differential amplifier 36 is given as follows; EQU i36=(Vin-m.multidot.Vout)/(R46+R48) (7)
wherein R46, R48 are resistances of the resistors 46, 48, respectively, and m is a signal feedback ratio defined by the resistance of the resistor 82.
From the equations (6) and (7), the following equation is obtained: EQU Vout/Vin=1/[m+S.multidot.C22.multidot.(R46+R48).multidot.I44/I28](8)
As is made clear from a comparison between the equations (1) and (8), these first to fifth filter circuits shown in FIGS. 1 through 5 have the same frequency characteristic.
The time constant of the fifth filter circuit, as shown in FIG. 5, can be arbitrarily set if the conversion ratio of the current conversion circuit 38 is adjusted through the control of the current I28 of the variable current source 28. The conversion ratio of the current conversion circuit 38 can be adjusted through the control of the current I44 of the variable current source 44, instead of the control of the current I28 of the variable current source 28. That is, the current source of the first differential amplifier 36 is made variable and the current source of the second differential amplifier 74 is made constant.
In the fifth filter circuit, as shown in FIG. 5, the variability of the time constant responds to the variable current source 28 (or the current source 44), but not to the resistors 46, 48 or the capacitor 22. As a result, the variability of the time constant does not respond to amplitude changes of the input signal Vin.
In the conventional filter circuits, as shown in FIGS. 1 to 5, the time constant of the filter characteristics is apt to differ from the designed value due to the inaccuracy of the resistances or the capacitances of the resistive elements and capacitive elements, e.g., the resistors 46, 48 and the capacitor 22. As a result, the time constant must be adjusted by the control of the current I28 and/or I44 of the current sources 28. 44. Further, the time constant is apt to vary due to the unstableness of the resistances or the capacitances of the resistive elements and capacitive elements. Therefore, such an adjustment is required to be made as the occasion may demand. However, when the filter circuit is fabricated in an IC configuration, the need for such an adjustment of the time constant is undesirable. This is because the IC requires an additional pin for receiving the control voltage Vc for this adjustment. In the prior art, there is no suitable means to automatically carry out this adjustment. In the filter circuit, as shown in FIG. 5, a means to correct by utilizing the equivalent resistance obtained by switching the capacitance C22 of the capacitor 22 is present. However, this circuit is unfavorable in terms of noise caused by the switching, and it cannot be used in an analog IC.